NRZ/CMI(III) CODE CONVERSION CIRCUIT

摘要

The apparatus includes a first D flip-flop (U1) for receiving NRZ data and synchronizing clock pulses to re-time them. An OR gate (U3) receives the output of the first D flip-flop (U1) and the synchronizing clock pulses to logic-add them and to generate space segment pulses. A first exclusive OR gate (U4) exclusively logic- adds the outputs of the first and second D flip-flop (U1)(U2) , and the second D flip-flop (U2) receives the synchronizing clock pulses of the NRZ data to alternately pick up only mark bits. A second exclusive OR gate (U5) exclusively logic-adds the outputs of a delay device (U6) and the second D flip-flop (U2), thereby outputting code pulses.