发明名称 PSEUDO ERROR GENERATING SYSTEM
摘要 PURPOSE:To easily evaluate the error processing by inverting the input of one of two duplex computing elements with firmware for generation of an error. CONSTITUTION:A computing element B 6 which uses the outputs of a register X 1 and a selector 5 as inputs performs the same operation as a computing element A 3. Thus the elements B 6 and A 3 are duplex in order to confirm the correct arithmetic result of the element A 3. A comparator 7 compares the arithmetic results of both elements A 3 and B 6 with each other and outputs a comparison error signal (b) when no coincidence is obtained between both arithmetic results. The selector 5 usually selects the value of a register Y 2 and also selects the output of an inverter 4 with a selection signal (a) obtained under the control of firmware. Thus the value of the register Y 2 is inputted to the element A 3, and the inverted value of the register Y 2 is inputted to the element B 6 respectively. As a result, no coincidence is obtained between the arithmetic results of both computing elements and the signal (b) is outputted from the comparator 7.
申请公布号 JPH04180134(A) 申请公布日期 1992.06.26
申请号 JP19900309613 申请日期 1990.11.15
申请人 NEC IBARAKI LTD 发明人 EDA YOSHINORI
分类号 G06F11/08;G06F7/00;G06F11/22 主分类号 G06F11/08
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