ASYNCHRONOUS INTERFACING CIRCUIT

摘要

The circuit includes a decoding section (30) for decoding address signals of a CPU to send the decoding signals to a control section and to enable an RTC chip. A control section (60) reads address signals and data signals from the RTC chip in accordance with the decoding signals of the decoding section (30), and supplies control signals to both an address buffering section (40) and a data buffering section (50) so as for the sections to store the data. Further, the control section (60) sends an access termination signal to a CPU, when the CPU completes the operation of accessing the RTC chip. The address buffering section (40) and the data buffering section (50) store address values and data values in accordance with the signals of the control section (60).