发明名称 CLAMP CIRCUIT
摘要 PURPOSE:To avoid the occurrence of an error and a step difference of an output signal with respect to a reference level by providing a changeover means through which an input signal is outputted for a clamp period and a 1st reference voltage is outputted for a signal period and integrating the output so as to clamp the input signal. CONSTITUTION:The clamp circuit is provided with a changeover means 5a through which an input signal is outputted for a clamp period and a 1st reference voltage 7a is outputted for a signal period, an impedance conversion means 8 reducing an output impedance of the changeover means 5a, an integration device 9 integrating the output, and a comparator 11 comparing the output of the integration device 9 with a 2nd reference voltage 10. In this case, the output impedance of the changeover means 5a is reduced by the impedance conversion means and then the output is inputted to the integration device 9. The integration device 9 integrates its input signal to eliminate the noise component of the signal. Thus, the occurrence of an error and a step difference in the reference level is avoided by clamping the input signal based on the output of the integration device 9.
申请公布号 JPH04132412(A) 申请公布日期 1992.05.06
申请号 JP19900254863 申请日期 1990.09.25
申请人 NEC CORP 发明人 AMANO NOBUTAKA
分类号 H03K5/007;H03K5/00 主分类号 H03K5/007
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