| 摘要 |
A linear feedback shift register comprises a shift register formed of first to (n)th flipflops cascaded in such a manner that an output of a (i)th flipflop is connected to an input of a (i+1)th flipflop, where 2</=n and 1</=i</=(n-1). First to (n)th output terminals are connected to outputs of the first to (n)th flipflops, respectively, and a clock terminal connected to a clock input of each of the flipflops. First to (n-1)th multiplexors of a "1-out-of-2" type are connected at their first input to a common preset value input terminal. Second inputs of the first to (n-1)th multiplexors are connected to the outputs of the first to (n-1)th flipflops, respectively. Each of the first to (n-1)th multiplexors has a control input connected to an individual control terminal. First to (n-1)th exclusive-OR gates are cascaded in such a manner that a first input of a (n-1)th exclusive-OR gate is connected to the output of the (n)th flipflop, a first input of an (i)th exclusive-OR gate is connected to an output of an (i+1)th exclusive-OR gate, and an output of the first exclusive-OR gate is connected to an input of the first flipflop. A second input of the (i)th exclusive-OR gate is connected to an output of the (i)th multiplexor. With this arrangement, a generator polynomial generated by the linear feedback shift register can be modified by controlling the multiplexors through the individual control terminals. <IMAGE> |
