| 摘要 |
<p>The semiconductor memory device of the present invention includes a sense amplifier for converting an electrical current flowing through a sense node (21) between a load (31) and a current limiting circuit (32,33) into an electrical voltage and for outputting the produced electrical voltage. The sense amplifier is constituted by plural stage amplifiers (22 to 24) each of which may be shorted across it input and output terminals. The amplifiers are set to the amplifying state, stage by stage, starting at the amplifier closest to the node (21), for overcoming problems concerned with noise superposition or an output delay caused by bit line overcharging. In a preferred embodiment, MOS transistors (35,32) for electrical discharging or precharging are provided in the bit line (BL) or the sense node (21) for speeding up the operation. <IMAGE></p> |
