| 摘要 |
PURPOSE:To shorten the test time at the time of the inspection of products by providing a test circuit outputting a level signal where logical values '1' and '0' corresponding to respective bits of an output port, are alternately repeated in a prescribed period after reset. CONSTITUTION:A reset signal 101 is inputted from an input terminal 51 to an AND circuit 3 through a delay circuit 1 and an invertor 2, and the output and a test signal 120 are inputted to an AND circuit 4. An output signal 105 from the circuit 4 is inputted to OR circuits 6 and 9 and a buffer 10. A write permitting signal 104 from CPU 5 is inputted and the output is inputted to an output latch 8 as the control signal. A clock 106 inputted from a terminal 54 is transmitted to a terminal 53 through the buffer 10, a data bus 201 and the output latch 8 only in a time zone when the signal 105 is in an H state, and the data on '1' or '0' is outputted. |
