| 摘要 |
A zero hold time data input cell is realized by employing a programmable data delay line containing a series of delay stages. Since each delay stage contributes only a fraction of the total data delay required, the rise/fall times of each data delay stage can be very fast, under all PVT (process/voltage/temperature) conditions. As a result, any amount of data delay can be provided at any data rate, while still allowing the delayed data waveform to make complete voltage excursions between the ground voltage and the power supply voltage. This capability prevents data dependent hold violations from occurring.
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