| 摘要 |
PURPOSE:To detect the fault, which can not be detected normally, of a bus transfer circuit by providing a clock control circuit to directly control a clock in the partial circuit of a logic circuit. CONSTITUTION:A control circuit 100, bus circuit 101 and clock control circuit 102 are provided. This added clock control circuit 102 is composed of OR gates 118 and 119 and inverter 120. In such a case, by controlling two-phase clocks phi1 and phi2 in the partial circuit of the logic circuit, the clocks phi1 and #2 supplied by the partial circuit of the logic circuit are fixed to a high level or a low level. Thus, since the clock in the partial circuit of the logic circuit can be controlled, it is possible to detect the fault, which can not be detected normally, of the bus transfer circuit. |
