| 摘要 |
The bus line (BL) is used for data transfer between a number of data transmitters (DW1...DWY) and data receivers (DP1...DRX) and is charged to an initial charge voltage level during a pre-charging phase, with subsequent charge voltage reversal in dependence on the digital information to be transmitted, via a rapid charge reversal circuit. The latter uses a trigger stage (TC) connected to the bus line (BL) to allow its rapid charging or discharging when a given trigger level is reached. Pref. the bus line (BL) is oivided into a series of partial bus lines (BLA,BLB...BLN), each coupled via a respective switch (SGA, SGB...SGN) to one input of a logic gate (LG) controlling discharge transistors (T1A,T1B...T1N) for rapid charge reversal of each partial bus line (BLA,BLB...BLN).
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