| 摘要 |
PURPOSE:To reduce the circuit scale by separating a bit coefficient into 2N and its deviation, multiplying data with them and adding and subtracting the result while a digit is matched. CONSTITUTION:A digital multiplier is a multiplier including the multiplication with a coefficient and provided with a multiplier section 1 in which an upper limit in a coefficient in (m+n+1) bits represented by a=2N+ or -epsilon(N=0,+ or -1,+ or -2,...;0<epsilon<<2N) is 2N<-m> or below and its setting accuracy is only epsilon in n-bit and it is multiplied with a digital signal (x), and with an adder section 2 outputting a multiplied value between the digital signal (x) and the coefficient (a) by adding or subtracting a least significant bit of the digital signal (x) and the least significant bit of the output of the coefficient while shifting them by (m+n) bits. Thus, a higher accuracy of multiplication is implemented with a small circuit scale. |
