| 摘要 |
PURPOSE:To switch a clock while maintaining a logic circuit in an operating state as it is by controlling the pulse width of the clock to be selectively outputted so as to satisfy a specified condition. CONSTITUTION:A clock selecting signal is synchronized to a timing signal by a D flip-flop FF 8 and further, by using two DFF 8, signals are obtained so as to be respectively synchronized to the start and end of the timing signal. H pulse width from the start to the end of the clock pulse to be outputted is made equal to the shorter H pulse width of the first or second clock or wider than this width and equal to the sum of adding the H pulse width of the first and second clock pulses or narrower than this sum, and L pulse width from the start to the end is made equal with the shorter L pulse width of the first or second clock or wider than this width and equal to the sum of adding the L pulse width of the first and second clocks or narrower than this sum. Therefore, without stopping the impression of power supply or the supply of the clock to the logic circuit, the clock can be switched to the clocks of various frequencies. |
