| 摘要 |
PURPOSE:To reduce an inductance component created by a wiring and the variation of the inductance by a method wherein respective I/O electrodes on a semiconductor chip are electrically connected to the respective electrode terminals of a header through through-hole which are so formed as to correspond to the respective electrodes of the chip and thick plating layers which fill the through-holes. CONSTITUTION:Source electrode 2, gate electrode 3 and drain electrode 4 on a semiconductor chip are linked with the rear of a semiconductor substrate 1 through through-holes 5 formed in the semiconductor substrate 1 and thick plating layer 6. When the chip is mounted on a microwave header 8, dielectric substrates 10 are formed on the sides of the I/O electrodes 12 and 13 of the header 8 and metallized patterns 11 are formed on the surfaces of the dielectric substrates 10 to form an impedance matching circuit. Not only the source electrode 2 but also the gate electrode 3 and the drain electrode 4 are electrically connected to the respective electrode terminals 12 and 13 of the header 8 with the through-holes 5 and the thick plating layers 6 filling the holes 5. therefore, the parasitic inductance component of a wiring can be substantially suppressed and the variation of the inductance can also be reduced. |
