| 摘要 |
PURPOSE: To minimize the dimension of a cell and to increase the mounting density at the same time by configuring a latch circuit with a stacked-type CMOS transistor, comprising trench-type transistors having capacitors cross- coupled capacitors in the inside. CONSTITUTION: A latch circuit 10 is constituted of two pairs of MOS transistors. That is to say, a pair is constituted of P-channel transistors 12 and 14, and a pair is constituted of N-channel transistors 16 and 18. Both first sources/drains 20 and 22 of the transistors 12 and 14 are connected to a power supply voltage point Vcc at the uppermost part. Similarly, first sources/drains 24 and 26 of the transistors 16 and 18 are coupled to a reference voltage point, which is the ground at the lowest part. Furthermore, a second source/drain 28 of the transistor 12 and a second source/drain 30 of the transistor 16 are connected. Similarly, a second source/drain 32 of the transistor 14 and a second source/ drain 34 of the transistor 18 are connected. The digital information is stored in first and second coupling points 36 and 42. |
