发明名称 |
DIGITAL SIGNAL PROCESSING |
摘要 |
For more convenient mechanisation, the modulo m reduction of a binary number P can be carried out by conditionally summing the modulo m reductions of a power series of two and then modulo m reducing the sum. The modulo m reductions of the series, called the 'residues' of the series, can be pre-calculated and stored but this may be inconvenient if they are long in terms of numbers of bits. Herein, the residues are calculated in sequence by a recursive process, each residue being calculated from the next preceeding one, this leading to a 'serial' arrangement for generating the residues which can be incorporated into a serial modulo m reduction unit. Such a serial modulo m reduction unit is convenient for implementation as an integrated circuit especially as part of an overall circuit for encryption and decryption of digital signals. |
申请公布号 |
EP0350278(A3) |
申请公布日期 |
1991.09.11 |
申请号 |
EP19890306804 |
申请日期 |
1989.07.04 |
申请人 |
BRITISH AEROSPACE PUBLIC LIMITED COMPANY;THE HATFIELD POLYTECHNIC |
发明人 |
GUPPY, JOHN R.;FINDLAY, PAUL A.;JOHNSON, BRIAN A. |
分类号 |
G06F7/72;G09C5/00;H04L9/30;(IPC1-7):G06F7/72 |
主分类号 |
G06F7/72 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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