Semiconductor memory circuit apparatus.

摘要

An improved RAM has a dummy word line (DWL) having the same pattern and same gate as the word lines provided RAM cells (101) in order to detect that one of word lines (WL1-WLn) is selected until the end of the word lines, then operate a sense amplifier (109). A transistor (T1) having the same W/L (W: channel width; L: channel length) as an output transistor (T1) in the RAM cell is connected in series between a transistor (T2) similar to a transfer gate (T2) in the RAM cell at the final stage and a ground voltage supply, for example, and receives an enable signal as its gate input. Provided between the transistor (T2) and a VDD voltage supply a transistor (T3) which has a different polarity from that of the second transistor (T1), and receives the enable signal as its gate input. Accordingly, the second and third transistors (T1, T3) constitute an inverter (151). The capacitance (C2) of the drain portion of this inverter is set close to the capacitance (C1) of the bus line on the RAM side, thereby adjust the dummy word line (DWL) and the word lines on the RAM circuit side to have the same transfer delay. If the drain capacitance (C2) on the dummy side corresponding to the bus line is adjusted slightly smaller than the bus line capacitance, the potential of the drain can be changed by this slight difference. This drain potential when detected can be used as a drive signal to drive the sense amplifier. Further, the signal traveling through the dummy word line can be used as a precharge signal.