| 摘要 |
Technologies are generally described herein generally relate to tunnel field-effect transistor (TFETs) structures with a gate-on-germanium source (GoGeS) on bulk silicon substrate for sub 0.5V (VDD) operations. In some examples, the GoGeS structure may include an increase in tunneling area and, thereby, a corresponding increases in the ON-state current ION. In order to achieve supersteep sub-threshold swing, both the lateral tunneling due to gate electric-field and the non-uniform tunneling at the gate-edge due to field-induced barrier lowering (FIBL) may be suppressed through selection of component dimension in the device structure. Example devices may be fabricated using CMOS fabrication technologies with the addition of selective etching in the process flow. |
