摘要 |
The frequency synthesiser circuit has a phase-locked loop with a controlled oscillator (1), a frequency divider (2) and a phase detector (3). A controlled switch (7, 8) allows the operating voltage for the frequency divider (2) and the phase detector (3) to be interrupted with the voltage for the control input of the oscillator (1) maintained by a capacitor (10), to maintain a stable oscillator frequency. Pref. the switch (7, 8) also allows the phase-locked loop to be interrupted between the phase detector output and the oscillator input. ADVANTAGE - Allows battery capacitance to be reduced.
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