| 摘要 |
A doppler video signal conditioning circuit comprising first, second and third buffers which respectively receive a voltage controlled oscillator signal, a second intermediate frequency signal and a second local oscillator signal from a missile' radar receiver. The buffered voltage controlled oscillator, second intermediate frequency and second local oscillator signals are then supplied to a doppler processing circuit. The doppler processing circuit processes these signals, providing at its output a reconstructed doppler video signal which includes a marker which is 20 kHz above the frequency the missile's radar is tracking. The doppler processing circuit provides the reconstructed doppler video signal to an analog-to-digital converter. The analog-to-digital converter digitizes the reconstructed doppler video signal before supplying the digitized signal to a frame controller. The frame controller assembles the digital data of the reconstructed doppler video signal into a plurality of telemetry frames with each frame having 1024 eight bit words. The eight bit words of each telemetry frame are then supplied to a parallel to serial shift register which converts each word from a parallel format to a serial format. The frame controller also generates timing signals and control signals for the analog-to-digital converter and the serial to parallel shift register.
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