| 摘要 |
PURPOSE:To increase the number of converted bits even when a high clock frequency is used, by counting a sequence of pulses of the 2nd clock signal during a period which corresponds to time width until the pulse of the 1st clock signal is detected. CONSTITUTION:The discharging of a capacitor C2 starts by a constant current from a constant current circuit 9, but the terminals J and K of a counter circuit 12 are held at ''H''s by a control circuit 13 at this time, thereby starting counting the pulse sequence of a clock signal P2. Once the output of a voltage comparator 10 changes from an ''L'' to the ''H'', the control circuit 13 inverts the terminals J and K of the counter circuit 12 from the ''H''s to the ''L''s to stop the counting operation. Then, the counter circuit 12 outputs a digital signal of eight-bit binary codes which vary in proportion to the extent of an error in quantization. |
