TIME DELAY CIRCUIT USING RESISTANCE MEANS

摘要

The circuit is capable of delaying time without any affects of voltage supply and ambient temperature variation to semiconductor element such as memory. This delayer is implemented by inserting a resistor (22) between logic gates (21)(23) which are CMOS inverter. The node voltage of (47) is decided by the resistance value of (22) and thus delay time can be regulated by (22). The resistance is placed under the power bussing or data bussing with insulators instead of directly inserting resistor between inverters. Therefore the size of the chip can be reduced, which is another merit. Doped multicrystalline silicon resistor or diffused resistor can be used in the circuit and their size decide pulsewidth of logic gate output signals.