| 摘要 |
Voltage step-up circuit for a non-volatile semiconductor memory which comprises a first series of an odd number of inverters (20), a second series of an even number of inverters, and a transmission grid (203) provided in the inverter of the pre-stage of each series of inverters in order to control the potentials applied to the p-channel and n-channel transistors of the inverter of the final stage, in such a way that the two transistors are not made to conduct simultaneously.
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