| 摘要 |
<p>PCT No. PCT/FR88/00042 Sec. 371 Date Aug. 16, 1988 Sec. 102(e) Date Aug. 16, 1988 PCT Filed Jan. 26, 1988 PCT Pub. No. WO88/05603 PCT Pub. Date Jul. 28, 1988.The CMOS circuit has n regions (20a) and p regions (32a) formed in a silicon substrate (2). A first mask is produced on the substrate, whose patterns (10a) mask the p regions (32a). A second mask (22a) is formed on the substrate masking the n regions (20a). The first mask, whose sides have in their upper part an inclined profile, can be selectively etched with respect to the second mask. The patterns of the first and second masks are separate and fix between them the location and width of the isolation trenches (24). The trenches are formed by etching the substrate and simultaneous etching takes place of the first mask and the substrate for forming in the upper part (24a) of each trench and in contact with the p regions, sides (26) inclined with respect to the upper surface of the substrate, so that the section of the trenches (24) widens towards said upper substrate surface.</p> |
