DATA READ CIRCUIT FOR SEMICONDUCTOR MEMORY

摘要

PURPOSE:To shorten the time required for equalizing a data line in the read cycle of data and to enable access at high speed by providing the first and second equalize pulse generating means and specifying the capacity load of a signal system to which the first and second equalize pulses are applied. CONSTITUTION:An equalize pulse PHIeq is supplied from the first equalize pulse generating circuit 41 to the gates of transistors Tr1, Tr2, Tr4-Tr6 and an equalize pulse PHIeq' is supplied from the second equalize pulse generating circuit 42 to the gate of a transistor Tr3 only. Since the equalize pulse generating circuit 42 is composed of logic circuits, which number is smaller than that of the equalize pulse generating circuit 41, the equalize pulse PHIeq' is established at timing earlier than the equalize pulse PHIeq. Thus, the pulse width of the PHIeq can be shortened and the data can be read out at high speed from a memory cell 11.