发明名称
摘要 PURPOSE:To transfer data efficiently between a video memory and a display of each processing element by exchanging data between a video bus and the video memory. CONSTITUTION:A pixel counter 4 shows an address of a video memory 5. When a pixel clock CLK is inputted under the condition where a signal WIND is under the condition of the logic ''1'', an AND circuit 25 supplies a clock to the pixel counter 4. When a clock is inputted, a counted value of the pixel counter 4 is counted up. When the signal WIND is in the logic ''1'', a counted value of the pixel counter 4 turns out an address of the video memory 5. Under the condition where a write-enable signal WE specifies writing, picture data on a video bus is written on the video memory 5. Then, when the signal WE specifies reading out, readout data from the video memory 5 are outputted to the video bus.
申请公布号 JPH0312346(B2) 申请公布日期 1991.02.20
申请号 JP19840038402 申请日期 1984.02.29
申请人 FUJITSU LTD 发明人 ISHIHATA HIROAKI;ISHII MITSUO;KAKIMOTO MASANORI
分类号 G06F15/16;G06F15/80;G06T1/20 主分类号 G06F15/16
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