| 摘要 |
PURPOSE:To reduce the number of used input and output pins of an LSI incorporating an operating circuit and to improve the integration degree and economize the hardware quantity, by transmitting different selecting signals in time division through the same address signal line. CONSTITUTION:An input register to an operating circuit 10 and an operation result storage register are selected by combinatins of plural fields F, SX, A, SY, etc. of one micro instruction. In this data processing device, a register address signal for selecting the operating circuit input register is transmitted in the first half of one machine cycle to operation registers 4-9 through a signal line 21, and a register address signal for selecting the operation result storage register is transmitted in the latter half to registers 4-9 through the same signal line 21. For example, one machine cycle is divided to four phases, and a register for source data is selected in the phase 0, and the operation is executed in phases 1 and 2, and the operation result is set to a destination register in the phase 3. |
