发明名称 HIGH EFFICIENCY PICTURE CODER
摘要 <p>PURPOSE:To improve the coding efficiency and the reduction picture quality in the case of reproduction of a reduced picture by providing a macro block processing means, and inter-field block processing means, an in-field block processing means and a block selection means. CONSTITUTION:A picture signal subject to 2:1 interlace scanning is inputted from an input terminal 1 and a macro block processing circuit 2 splits the signal into plural macro blocks each comprising 8-picture element X 16-line. Then a moving still deciding circuit 3 decides whether or not a video image in each macro block is moved or at standstill and when it is decided that the picture is at standstill, switches 4, 7 are connected to an inter-field block processing circuit 5. When it is decided that the picture is moving, the switches 4, 7 are connected to in-field block processing circuit 6. Thus, the forming method of the block is switched adoptively in the unit of macro blocks to improve the coding efficiency and when a reduced picture is reproduced, the quality of the reduced picture is improved.</p>
申请公布号 JPH031688(A) 申请公布日期 1991.01.08
申请号 JP19890135370 申请日期 1989.05.29
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 KAMIKURA KAZUTO;SAWADA KATSUTOSHI
分类号 H04N19/60;H03M7/30;H04N19/00;H04N19/119;H04N19/137;H04N19/176;H04N19/46;H04N19/51;H04N19/625;H04N19/70;H04N19/85 主分类号 H04N19/60
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