| 摘要 |
A data acquisition system suitable for use in a SAR type A/D converter has a metastable sense feature capable of sensing and resolving a metastable condition in the input latch structure of a SAR in order to enable the acquisition of each bit of a digital output word within no more than two clock cycles. In one embodiment the data acquisition system includes a master latch having an input for receiving a digital input signal and a plurality of input latches wherein the inputs of the input latches are coupled together and to the output of the master latch. A sense latch is further included wherein the input of the sense latch is coupled to the output or sense node in the master latch for sensing a metastable condition with the master latch. A plurality of secondary latches is included wherein the inputs of the secondary latches are coupled together and to the output of the sense latch. A logic circuit coupled to the outputs of the input latches and to the outputs of the secondary latches passes the outputs of the input latches directly to a system output if no metastable condition is sensed in the master latch. If a metastable condition is sensed in the master latch, the current bit output is forced to a logic one, more significant bit outputs are unaffected, and less significant bit outputs are forced to a logic zero, thus terminating the data acquisition of the current digital input signal.
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