Parallel bit stream interface with automatic clock phasing - produces clock signals for further processing by division of integral multiple of input bit stream frequency

摘要

A transition detector (WD) comprising two D flip-flops (DF1,DF2) in series and an Exclusive-OR gate (EX) is connected to e each input (D1-Dn) of the digital interface. A bit-phase-dependent setting pulse (S) is addressed to each multiplexer/flip-flop (MX1-MX4) of a frequency divider (SR) working on the principle of the Johnson counter. The final stage (MX4) gives a bit clock output (Tn) adjusted automatically to the phase of the incoming bit stream. ADVANTAGE - Comparatively simple interface achieves automatic phase adjustment irrespective of propagation time, avoiding scanning of transmitted bit at its beginning or end.