| 摘要 |
<p>PURPOSE:To obtain a pulse with narrow pulse width and high pulse width recision by using the combination of a latch circuit with gate and a logical operation circuit. CONSTITUTION:A logical signal which level-changes by the leading edge and the trailing edge of an input signal (a) and the inverse of (a), and by the leading edge and the trailing edge of a latch output (b) and the inverse of (b) in the latch circuit 14 with gate 14 as the output (e) of the logical operation circuit 11 consisting of AND gates 15 and 16 and a NOR gate 17. Although the logical signal comes to the charge/discharge switching signal of a charge/discharge circuit 3, the charge/discharge cycle of the charge/discharge circuit 3 becomes shorter when the pulse widths of the input signal (a) and the inverse of (a0 are short, and the occurrence of an output pulse from a hysteresis comparator 8 is prevented. The pulse width of an output pulse (g) is decided by a delay time in the feedback logical loop of the output pulse (g). Thus, the variance is prevented from occurring in the pulse width of an output signal by the pulse widths of the input signals, and the output signal having the narrow pulse width and the high pulse width precision.</p> |
