| 摘要 |
<p>A gate array semiconductor integrated circuit includes a plurality of input/output cells (12), an input/output circuit (13, 14), and a bias circuit (15). The plurality of input/output cells (12) are arranged around an internal logic gate (11). The input/output circuit (13, 14) is formed by an aluminum master slice of the input/output cells (12) and performs an input/output operation for the internal logic gate (11). The bias circuit (15) is formed by the aluminum master slice of the input/output cells (12) to supply a predetermined bias voltage to the input/output circuit (13, 14).</p> |
