发明名称 DIGITAL PLL APPARATUS FOR PARALLEL OPERATION SYSTEM
摘要 PURPOSE:To reduce follow-up phase difference between a plurality of controllers by providing a three-phase/two-phase converting means, a two-phase feedback signal producing means, means for detecting phase difference between three- phase input and feedback signal, means for producing pulse proportional to the phase difference, first and second counters, a phase compensation operating means, and an adding means. CONSTITUTION:A three-phase/two-phase converter 10 converts a three-phase input signal into a two-phase signal which is then applied onto a phase difference detecting circuit 11, and a feedback signal produced from a data generator 18 is applied onto the phase difference detecting circuit 11. The phase difference detecting circuit 11 detects the phase difference between the three-phase input signal and the feedback signal and produces pulses 101 having frequency proportional to the phase difference, then the pulses are counted by a phase counter arranged in its controller and the counter is cleared when the count reaches to the frequency of commercial power source. A high speed correction operating circuit 16 operates the phase correction amount which is added in an adder 17 for every constant period sampling time. By such arrangement, follow-up phase difference between a plurality of controllers can be reduced.
申请公布号 JPH02262845(A) 申请公布日期 1990.10.25
申请号 JP19890050893 申请日期 1989.03.02
申请人 TOSHIBA CORP 发明人 TAKEUCHI HIROSHI
分类号 H02J3/38;H02M7/493;H03L7/06 主分类号 H02J3/38
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