<p>A programmable logic array circuit which has a decoder, a sense amplifier and a latching circuit. The decoder decodes an instruction code into an output signal after a first precharge timing. The latching circuit latches the output signal from the decoder immedeately before a second precharge timing. The gate circuit controls an output operation of the latching circuit in response to a prescribed timing signal.</p>
申请公布号
EP0391379(A2)
申请公布日期
1990.10.10
申请号
EP19900106416
申请日期
1990.04.04
申请人
OKI ELECTRIC INDUSTRY CO., LTD.
发明人
TANAGAWA, KOUJI, C/O OKI ELECTIRC INDUSTRY CO.,LTD