发明名称 Data processor with interrupt control - allows interruption of central processing unit in response to direct memory access command
摘要 The data processor has a main memory (300) holding the data processing information, a central processing unit (101) and an interrupt control (102) for the latter. The control (102) responds to an interrupt command supplied by a direct memory access control (103) for the main memory (300). Pref. a selection circuit (104) has a logic device receiving signals from a serial communication control (106) and allowing transfer of the READY signals, the direct memory access commands and the interrupt commands. ADVANTAGE - Effective utilisation of processing hardward.
申请公布号 DE4010311(A1) 申请公布日期 1990.10.04
申请号 DE19904010311 申请日期 1990.03.30
申请人 MITSUBISHI DENKI K.K., TOKIO/TOKYO, JP 发明人 KONDO, HIROYUKI;NAKAO, YUICHI;KOYAMA, KAZUMI, ITAMI, HYOGO, JP
分类号 G06F13/00;G06F13/32;H04L29/10 主分类号 G06F13/00
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