| 摘要 |
PURPOSE:To improve the use efficiency of a bus and registers by sending a desired field select signal to a pertinent bus driver control circuit from a field select signal generating part at the time of transferring data and sending this select signal to a register control circuit on the data loading side. CONSTITUTION:When data of respective fields are transferred from bus drivers 3-1 and 3-2 of a memory 1 to divided registers 2-1 and 2-2 of a register 2, the field select signal to select fields of bus drivers 3-1 and 3-2 is sent to a bus driver control circuit 5 from a field select signal generating part 8, and the field select signal to select registers 2-1 and 2-2 is sent to a register control circuit 7. Then, data of these fields are sent to the bus by the bus driver control circuit 5, and the register control circuit 7 sends a data loading signal to registers 2-1 and 2-2. Thus, a part of data is simultaneously transferred to another register to improve the use efficiency of the bus and registers. |
