| 摘要 |
PURPOSE:To attain quick test of a multi-stage synchronous counter by providing a test data generating circuit outputting a test data and a selection circuit receiving the test data and applying an output to the generating circuit selectively. CONSTITUTION:A test data generating circuit 1 outputs a test data TDATA whose effective binary data bit number is increasing in response to the application of a clock CLK. A multi-stage synchronous counter 3 in 10-bit outputs 10 sets of data TDATA only in response to the clock CLK. A selection circuit SEL 2 outputs the data TDATA to a counter 3 from the circuit 1 in the case of an enable test signal TEST. The counter 3 inputs the data TDATA to a data input terminal of each stage of circuits to apply the operation in response to the data TDATA. As a result, in the case of the counter 3, for example, number of times of the test is decreased to 10 thereby reducing the test time. |
