| 摘要 |
<p>PURPOSE:To eliminate the manual setting work of a clock distributor at the time of designing a hierarchy by automatically synthesizing a clock signal distributor after the hierarchy is developed, and distributing the clock signals again so as not to generate a clock skew. CONSTITUTION:A clock signal distributor synthesizing means 6 synthesizes the logical connecting information of the clock signal distributor based on stage number information 15 and distributed signal number information 16, and logical connecting information 17 of the synthesized clock signal distributor is transferred to a clock signal re-distributing means 7. The clock signal redistributing means 7 re-distributes the clock signal based on logical connecting information 18 stored into a logical connecting information storing means 1 and the logical connecting information 17 of the clock signal distributor, prepares logical connecting information 19 of a new logical circuit, and transfers the signal to a logical connecting information storing means 8. Thus the clock skew can be prevented from being generated, and labor and a time at the time of designing the hierarchy is made unnecessary.</p> |
