发明名称 |
Pre-charge circuit with a bipolar transistor |
摘要 |
An output signal of a logic portion is inputted to the gate of FET inside an output buffer portion to inverse the signal polarity by this FET and is outputted through a bipolar transistor effecting an emitter follower operation or the like. An FET controlled by a clock signal is disposed between the base of the bipolar transistor and the ground and an FET which is turned ON during a pre-charge operation and when the bipolar transistor is OFF during logic calculation is disposed between the emitter and the ground so as to short-circuit the emitter and the ground during the pre-charge operation. In this manner, higher operation speed, higher integration density and high operation margin can be accomplished without losing the characteristic features of a Bi-CMOS dynamic logic circuit in its high operation speed and low power dissipation.
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申请公布号 |
US4950925(A) |
申请公布日期 |
1990.08.21 |
申请号 |
US19880246196 |
申请日期 |
1988.09.19 |
申请人 |
HITACHI, LTD. |
发明人 |
DOI, TOSHIO;HAYASHI, TAKEHISA;ISHIBASHI, KENICHI |
分类号 |
H03K17/567;H03K19/017;H03K19/08;H03K19/0944;H03K19/096 |
主分类号 |
H03K17/567 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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