发明名称 HALBLEITERVORRICHTUNG MIT VERRINGERTER KAPAZITIVER BELASTUNG UND DEREN HERSTELLUNGSVERFAHREN.
摘要 There is provided a semiconductor device which comprises device regions and isolation regions to isolate the device regions from each other on a semiconductor substrate, wherein field insulators are formed in the isolation regions and conduction layers for wiring are formed above the field insulators. An additional impurity buried layer having an opposite conductivity to the semiconductor substrate is formed under the field insulators. Therefore the first capacitance element is composed of the conductive layer, the impurity buried layer, and the field insulator therebetween. The second capacitance element is composed of the impurity buried layer, the semiconductor substrate, and a PN junction layer therebetween. Thus the first capacitance element and the second capacitance element are connected in series.
申请公布号 DE3672032(D1) 申请公布日期 1990.07.19
申请号 DE19863672032 申请日期 1986.09.25
申请人 KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP 发明人 NOGUCHI, TATSUO C/O TOSHIBA HIYOSHI RYO, YOKOHAMA-SHI KANAGAWA-KEN, JP
分类号 H01L21/8234;H01L21/768;H01L23/522;H01L23/64;H01L27/02;H01L27/088;H01L29/06;(IPC1-7):H01L29/06 主分类号 H01L21/8234
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