| 摘要 |
An output clock signal is synchronized with predetermined phase accuracy relative to an internal stable frequency reference clock signal upon the application of a transition of an asynchronous event signal. A plurality of phase shifted versions of the reference clock signal are derived. Upon the occurrence of the asynchronous signal, the states of the phase shifted versions are sampled, and that information is utilized as a code to select one of the phase shifted versions from which the output clock signal is derived. Synchronization occurs rapidly within the metastable settling time of the flip-flops of a register which sample or decode the states of the phase shifted versions, or by logical gating arrangements which avoid the necessity for considering the metastable signal. Synchronization is typically obtainable in less than the period of one reference clock signal. |
