| 摘要 |
PURPOSE:To perform a simple digit matching process at high speed for an operand in such a case of a divisor has no regular form and at the same time the mantissa part of the dividend is larger than that of the divisor by carrying out all digit matching processes during execution of a division after the right shift of the dividend. CONSTITUTION:The output of a reading sign subtractor 26 is stored in a shift count register 6, and the result obtained by shifting the output of a fixed point register A2 to the right via an extension shifter 9 is stored again in the register A2. In such a case, a mantissa result selector 29 is set under a left 2-digit shift mode in case a fixed point comparator 7 decides that the contents of the register A2 are smaller than those of a fixed point register B3. At the same time, '-2' is stored in an exponent correction value register 18 and the output of an exponent result register 15 is corrected by an exponent correction circuit 16. This corrected output is stored again in the register 15. As a result, all digit matching processes can be carried out during execution of a division after the dividened is shifted to the right. Then, the average executing time of division can be shortened. |
