发明名称 |
Digital data processor with fault tolerant peripheral bus communications |
摘要 |
A fault-tolerant digital data processing system comprises at least a first input/output controller communicating with at least one peripheral device over a peripheral device bus. The peripheral bus includes first and second input/output buses, each having means for carrying data, address, control, and timing signals. The input/output controller includes an element for applying duplicate information signals synchronously and simultaneously to the first and second input/output buses for transfer to the peripheral device. The input/output controller further includes a bus interface element for receiving, in the absence of fault, duplicative information signals synchronously and simultaneously from the first and second input/output buses.
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申请公布号 |
US4926315(A) |
申请公布日期 |
1990.05.15 |
申请号 |
US19870079297 |
申请日期 |
1987.07.29 |
申请人 |
STRATUS COMPUTER, INC. |
发明人 |
LONG, WILLIAM L.;WAMBACH, ROBERT F.;BATY, KURT F.;LAMB, JOSEPH M.;MCNAMARA, JOHN E. |
分类号 |
G06F13/00;G06F1/04;G06F3/00;G06F11/00;G06F11/07;G06F11/10;G06F11/14;G06F11/16;G06F11/18;G06F11/20;G06F11/22;G06F13/36;G06F13/42 |
主分类号 |
G06F13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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