发明名称 TEST PATTERN GENERATOR
摘要 PURPOSE:To obtain a high fault detection rate even for a CMOS circuit by switching a control signal C1 and providing a multistage feedback type shift register. CONSTITUTION:A feedback shift register which makes a rightward shift by switching the control signal C1 and a feedback register which makes a leftward shift and has the same generating polynomial are realized. Both those shift registers are used as the generator to, so that data that two successive circuits 112 to be test input possibly at time (t) are '00', '10', and '01', or three kinds. Further, pairs of two out of the three patterns are generated for the inputs of all circuits 112. Thus, pairs of two patterns can be generated, so the high fault detection output can be expected.
申请公布号 JPH02102469(A) 申请公布日期 1990.04.16
申请号 JP19880256193 申请日期 1988.10.11
申请人 NEC CORP 发明人 YOSHIDA MASAAKI
分类号 G01R31/3183;G01R31/28;G06F11/22;H01L21/822;H01L27/04 主分类号 G01R31/3183
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