| 摘要 |
The peak value of the vertical synchronous signal determining the character width in the CRT controller is programmed with 4 or 8 bit so that the clock signal of the address counter has a duty ratio of 50% as well as generating other control signal. The generator comprises input signal control circuits (1,3,5), a clock signal control circuit (7), D flip-flops (2,4,6), inverters (IV1-8), OR gates (OR1-4), AND gates (AD1-14), and a XOR gate (EX1).
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