| 摘要 |
PURPOSE: To minimize the delay effect caused by the capacitance while keeping a low power level by using an inverter means which is connected between a junction and the gate of an FET. CONSTITUTION: An inverter means 22 is connected to the gate of an FET 23 from a junction 16. Thus, the conductivity of the FET 23 which is completely turned on in its initial state is imnediately reduced when the output voltage (output 12 and junction 16) reaches a desired level, i.e., the threshold level of an FET 22'. The signal of the means 22 functions to reduce the conductivity of the FET 23 in the due connection which includes the indirect circuit paths more than the direct connection secured to the gate. In such a constitution, a fast operating speed is assured in comparison with a silicon CMOS or a GaAsDCFL (gallium arsenide directly coupled FET gate). |
