发明名称 Variable length data processing apparatus.
摘要 <p>Variable length data stored in a RAM (3) are sequentially read out by designating their addresses. It is detected whether or not the readout data is a code indicating a delimitation of, e.g., a word block, record block, file block, or the like. If it is detected that the readout data is a code indicating a delimitation, an address at that time is latched, thus forming an address table based on the latched address. The address table thus formed is utilized upon retrieval of data in the RAM, thus allowing high-speed data access.</p>
申请公布号 EP0350929(A2) 申请公布日期 1990.01.17
申请号 EP19890112869 申请日期 1989.07.13
申请人 CASIO COMPUTER COMPANY LIMITED 发明人 KOMURO, JUNICHI PAT.DEP.DEV.DIV. HAMURA R&D CENT.;SATO, TETSUYA PAT.DEP.DEV.DIV. HAMURA R&D CENT.;HIDAKA, NORIHIRO PAT.DEP.DEV.DIV. HAMURA R&D CENT.
分类号 G06F12/04 主分类号 G06F12/04
代理机构 代理人
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