发明名称 PACKET DATA TRANSMISSION AND MEMORY STORAGE SYSTEM
摘要 PURPOSE:To improve the utilizing efficiency of a buffer memory by storing a packet data continuously without any gap into a buffer memory and using other means so as to provide sections of packet data. CONSTITUTION:The packet data outputted from an output circuit 1-3 is stored in a memory 1-1 through a packet data line 1-5. The packet data in the memory 1-1 is processed and decreased, but if packet data much more than the decrease are transferred from the packet data line, the memory is saturated. Thus, number of idle memories is informed from the memory 1-1 to a memory monitor circuit 1-2 through an idle memory number display signal line 1-7 and if the memory monitor circuit 1-2 estimates the production of saturation of the memory 1-1 by the information, a congestion control signal is transferred to the signal line 1-6. When the congestion control signal is received, the output control circuit 1-4 outputs the output inhibit signal to the signal line 1-8 and the output of the packet data from the output circuit 1-3 is stopped. Thus, the saturation of the packet data is prevented.
申请公布号 JPH01296740(A) 申请公布日期 1989.11.30
申请号 JP19880125705 申请日期 1988.05.25
申请人 HITACHI LTD 发明人 OZAKI NAOHIKO;AMADA EIICHI
分类号 G06F13/38;G06F13/00;H04L12/801;H04L12/911 主分类号 G06F13/38
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