| 摘要 |
In the operation of a highly integrated wavefront array processor having nxm processor cells arranged in n rows and m columns, an instruction code is shifted respectively, in hoirzontal and vertical directions between adjacent processor cells from one processor cell to the respective next horizontally and vertically adjacent processor cell. A first group of n row selection bits and a second group of m column selection bits are selectively shifted through the processor cell array to release certain processor cells for the execution of the instructions.
|
