| 摘要 |
<p>PURPOSE:To prevent malfunction due to a clock skew by a method wherein a clock generating device is arranged on the almost central part of a chip, wirings to feed the output of the clock generating device are arranged and wired in the interior of the chip in a lattice type and the clock skew in each logical device is made sufficiently small. CONSTITUTION:A wiring (a) is outputted from an external terminal 6 of a clock and is inputted in a clock generating device (means) 8. A clock pulse is subjected to waveform shaping in this device 8 and is outputted to a horizontal wiring (y3) and a vertical wiring (x3) through buffers to feed to each logical device. Wirings of the clock, vertical wirings x0, x2, x3, x4, x5 and x6 and horizontal wirings y0, Y1, Y3, y4, Y5 and y6, are provided in the interior of a chip 2 in a lattice type. Hereupon, a clock skew in each logical device is generated to the maximum on the central part and peripheral part of the chip 2. A rise of the clock is earliest on the central part of the chip and the clock rises later on the peripheral part in such a way as to draw concentric circles centering around there. The clock skew is hardly generated on the peripheral part.</p> |
