| 摘要 |
PURPOSE:To secure the stable and high speed action of a semiconductor IC by providing a second holding means which holds a logical level signal at the timing of a clock signal and which outputs the holding value to a holding means. CONSTITUTION:The holding circuit 27 consisting of TTR25 and an invertor 26 is provided immediately before the holding circuit 24 consisting of a transfer transistor(TTR)21 and an invertor 23. When the clock signal phi is inputted to the gate of TTR25, an input signal IN is transmitted to the circuit 24 through the circuit 27. At that time, the transfer timing of TTR21 is delayed from the signal but the timing that the signal IN is held by the circuit 27 coincides with the rise of the signal phi. Namely, prescribed non-overlap is secured between the timing that the logical level of the signal IN is decided and that of the signal phi. Even if non-overlap between the transfer timing of TTR21 and the signal phi reduces, transmission data of TTR21 is data decided in the circuit 27, and the logical level of the signal IN which is always decided is held in the circuit 24. |
